Pack-Error FPGA zu Klein: Wie optimieren?

Liebe Leute,

nach den letzten Paar Änderungen (eine FIFO mehr) in meiner VI ist die Kompilierzeit von einigen 10 Minuten gleich auf über eine Stunde explodiert. Zusätzlich gibt es jetzt einen Fehler beim Mappen.

Ich habe ein Schieberegister mit einem Integer. Abhängig von seinem aktuellen Wert, werden gewisse Code-Blöcke durchgeführt.
Es steht quasi fest, dass diese Blöcke nacheinander ausgeführt werden, aber es sollen einstellbare viele Leertakte dazwischen liegen können.

Habt ihr eine Idee, wie ich das optimieren kann? Oder sind 2 FIFOS sowieso vielzuviel?

Ich habe die FPGA PCI-7813R.

Viele Grüße,
Robert


Fehler beim Kompilieren:


ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.

If the slice count exceeds device resources you might try to disable register
ordering (-r). Also if your design contains AREA_GROUPs, you may be able to
improve density by adding COMPRESSION to your AREA_GROUPs if you haven't done
so already.

NOTE: An NCD file will still be generated to allow you to examine the mapped
design. This file is intended for evaluation use only, and will not process
successfully through PAR.

This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).

Design Summary:
Number of errors: 1
Number of warnings: 152
Logic Utilization:
Number of Slice Flip Flops: 10,383 out of 28,672 36%
Number of 4 input LUTs: 26,914 out of 28,672 93%
Logic Distribution:
Number of occupied Slices: 79,538 out of 14,336 554% (OVERMAPPED)
Number of Slices containing only related logic: 76,374 out of 79,538 96%
Number of Slices containing unrelated logic: 3,164 out of 79,538 3%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 158,127 out of 28,672 551% (OVERMAPPED)
Number used as logic: 26,914
Number used as a route-thru: 137
Number used for Dual Port RAMs: 131,072
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 4

Number of bonded IOBs: 94 out of 484 19%
IOB Flip Flops: 53
Number of Block RAMs: 32 out of 96 33%
Number of GCLKs: 2 out of 16 12%

Total equivalent gate count for design: 19,295,483
Additional JTAG gate count for IOBs: 4,512
Peak Memory Usage: 2027 MB

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